Researchers at EPFL have combined the fields of low-power chip design,
The system boasts a 256-channel high-resolution sensor array and an energy-efficient machine learning processor, enabling the efficient extraction and categorization of a wide range of biomarkers from real patient data and in vivo animal models of disease. This results in a high level of
Efficiency, scalability and versatility
NeuralTree works by extracting neural biomarkers – patterns of electrical signals known to be associated with certain neurological disorders – from brain waves. It then classifies the signals and indicates whether they warn, for example, of an impending epileptic seizure or parkinsonian tremors. If a symptom is detected, a neurostimulator – also located on the chip – is activated, sending an electrical pulse to block it.
Shoaran explains that NeuralTree’s unique design gives the system an unprecedented level of efficiency and versatility compared to the past. The chip has 256 input channels, compared to 32 for previous machine learning embedded devices, allowing more high-resolution data to be processed on the implant. The chip’s area-efficient design means that it is also extremely small (3.48 mm2), which gives it great potential for scalability to multiple channels. The integration of an “energy-aware” learning algorithm – which penalizes features that consume a lot of power – also makes NeuralTree highly energy-efficient.
In addition to these advantages, the system can detect a wider range of symptoms than other devices, which until now have focused primarily on the detection of epileptic seizures. The chip’s machine learning algorithm was trained on datasets from both epilepsy and Parkinson’s disease patients and accurately classified pre-recorded neural signals from both categories.
“To our knowledge, this is the first demonstration of parkinsonian tremor with an on-chip classifier,” says Shoaran.
Shoaran is passionate about making neural interfaces more intelligent to enable more effective disease control, and she is already looking ahead to further innovations.
“Ultimately, we can use neural interfaces for many different disorders, and we need algorithmic ideas and advances in chip design to make this happen. This work is very interdisciplinary, and therefore also requires collaboration with laboratories such as the Laboratory for Soft Bioelectronic Interfaces, which can develop state-of-the-art neural electrodes or laboratories with access to high-quality patient data.”
As a next step, she is interested in enabling algorithmic updates on the chip to keep up with the evolution of neural signals.
“Neural signals change, and over time the performance of a neural interface will decrease. We’re always trying to make algorithms more accurate and reliable, and one way to do that is to enable on-chip updates or algorithms that can update themselves.
References: “NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC” by Uisub Shin, Cong Ding, Bingzhao Zhu, Yashwanth Vyza, Alix Trouillet, Emilie CM Revol, La St. Mahsa Shoaran , 29 September 2022, IEEE Journal of Solid-State Circuits (JSSC).
“A 256-channel 0.227 µJ/class versatile brain activity classification and closed-loop neuromodulation SoC with 0.004 mm2-1.51 µW/channel Fast-Settling Highly Multiplexed Mixed-Signal Front-End” by Uisub Shin, Laxmeesha Somappa, Cong Ding, Yashwanth Vyza, Bingzhao Zhu, Alix Trouillet, Stephanie P. Lacour, and Mahsa Shoaran, 127 March 2020 . IEEE International Solid State Circuits Conference (ISSCC).